1. Field of the Invention
The present invention relates in general to ESD avoiding circuits, and more particularly, to the ESD avoiding circuits based on the ESD detectors in a feedback loop.
2. Description of the Prior Art
Since the complementary metal-oxide semiconductor (CMOS) production technology has advanced well into the deep-submicron and nanometer scale, integrated circuit (IC) performance has risen correspondingly. Nowadays, many integrated circuits are guided into mass production by the CMOS process. Some advanced process technologies for scaling-down device areas within integrated circuits, such as thinner gate-oxide and shallower drain/source, can effectively increase the integration and improve the characteristics of the devices. However, these advanced process technologies also significantly sacrifice the electrostatic discharge (ESD) robustness of the integrated circuit. Therefore, the ESD is more likely to become a bottleneck in the mass production yield rate of integrated circuits.
Please refer to FIG. 1, which is a schematic circuit diagram showing the structure of a prior art ESD protection circuit in an integrated circuit 100. The integrated circuit 100 comprises a connection pad 101, an input resistor 108, an internal circuit 120, a power clamp circuit 130, an input ESD protection circuit 105, and an input inverter 110. The input ESD protection circuit 105 comprises an NMOS transistor 106 and a PMOS transistor 107. The input ESD protection circuit 105 functions to perform an ESD protecting process between the connection pad 101 and a power terminal 190 as well as between the connection pad 101 and a ground terminal 195. The power terminal 190 and the ground terminal 195 can be a power route and a ground route respectively in the integrated circuit 100.
The power clamp circuit 130 functions to perform an ESD protecting process between the power terminal 190 and the ground terminal 195. The input inverter 110 comprises an NMOS transistor 111 and a PMOS transistor 112. The input inverter 110 is coupled between the input resistor 108 and the internal circuit 120. The resistor 108 in conjunction with the MOS capacitors of the MOS transistors 111, 112 functions to act as a resistor-capacitor circuit for providing a further ESD protection. The ESD protection circuit 105 and the power clamp circuit 130 are utilized to protect the internal circuit 120 based on discharging the ESD induced current. That is, when an ESD event occurs to the connection pad 101, the power terminal 190 or the ground terminal 195, the NMOS transistor 106, the PMOS transistor 107 or the power clamp circuit 130 is turned on or activated to efficiently guide any ESD induced current into a bypass path instead of into the internal circuit 120.
However, when the internal circuit 120 comprises a programmable circuit and a burning signal for programming the programmable circuit is furnished via the connection pad 101, the prior art ESD protection circuit of the integrated circuit 100 is not compatible with the programming requirement in that a parasitic diode structured by the junction between the drain and the channel well of the PMOS transistor 107 will clamp the voltage range of the burning signal within the supply voltage Vdd at the power terminal 190.
Please refer to FIG. 2, which is a schematic circuit diagram showing the structure of a prior art ESD protection circuit in an integrated circuit 200 with programmable functionality. It is obvious that the PMOS transistor 107 in FIG. 1 is removed so that the voltage range of the burning signal at the connection pad 101 is allowed to be greater than the supply voltage Vdd. The protection functionality concerning the PMOS transistor 107 is then replaced by the functional operation concerning the parasitic transistor of the NMOS transistor 106 in conjunction with the power clamp circuit 130. Accordingly, both the ESD protection circuits shown in FIG. 1 and FIG. 2 perform an ESD protecting process based on discharging the ESD induced current. However, when the amount of charges being accumulated instantaneously at the connection pad 101 is so great that even the ESD protecting process cannot release the accumulated charges soon enough, the ESD induced current can be furnished to the internal circuit 120, which will cause the internal circuit 120 to be damaged by the ESD induced current.